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Adding SPI & AXI to NEORV32 Design

ejaaskel.dev · published 20 May 2025

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Links from this post

Link
Host
https://en.wikipedia.org/wiki/Clock_domain_crossing
en.wikipedia.org
https://github.com/zephyrproject-rtos/zephyr/commit/0366df369b8a118f9b1cb24693541b2209b6ae58
github.com
https://stnolting.github.io/neorv32/
stnolting.github.io
https://github.com/stnolting/neorv32/blob/main/sw/example/demo_gpio/main.c
github.com
https://docs.amd.com/r/en-US/ug896-vivado-ip/COE-File-Syntax
docs.amd.com
https://www.allaboutcircuits.com/technical-articles/spi-serial-peripheral-interface/
allaboutcircuits.com
https://five-embeddev.com/quickref/interrupts.html
five-embeddev.com
https://docs.zephyrproject.org/latest/kernel/services/interrupts.html
docs.zephyrproject.org
https://nandland.com/lesson-13-metastability/
nandland.com
https://nandland.com/lesson-15-what-is-a-block-ram-bram/
nandland.com
https://zipcpu.com/blog/2022/05/07/learning-axi.html
zipcpu.com
https://adaptivesupport.amd.com/s/article/1053914?language=en_US
adaptivesupport.amd.com
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