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Why aren't my two Cortex-A9 cores cache coherent?

thejpster.org.uk · published 22 August 2026

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I decided to make an 1980's Home Computer in Rust - Part 1 Read at the source ↗

thejpster.org.uk

https://git.thejpster.org.uk/thejpster/mcb2130-rs

git.thejpster.org.uk

https://soc.terasic.com

soc.terasic.com

https://misterfpga.org/

misterfpga.org

https://github.com/rust-embedded/aarch32/tree/main/examples

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https://github.com/ferrous-systems/rust-training/tree/main/example-code/qemu-aarch32v8r

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https://github.com/ferrous-systems/s32z2-rust-demo

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github.com

https://crates.io/crates/aarch32-rt

crates.io

https://crates.io/crates/neotron-loader

crates.io

https://en.wikipedia.org/wiki/Motorola_S-record

en.wikipedia.org

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crates.io

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docs.rs

https://support.arm.com/documentation/ddi0406/c/Application-Level-Architecture/Application-Level-Memory-Model/Memory-types-and-attributes-and-the-memory-order-model/Device-and-Strongly-ordered-memory?lang=en

support.arm.com

https://en.wikipedia.org/wiki/Modified_Harvard_architecture

en.wikipedia.org

https://support.arm.com/documentation/ddi0406/c/Application-Level-Architecture/Application-Level-Memory-Model/Memory-types-and-attributes-and-the-memory-order-model/Normal-memory

support.arm.com

https://support.arm.com/documentation/ddi0246/h

support.arm.com

https://support.arm.com/documentation/100486/0401/snoop-control-unit

support.arm.com

https://support.arm.com/documentation/ddi0407/i/snoop-control-unit/scu-registers/scu-control-register?lang=en

support.arm.com

https://support.arm.com/documentation/100486/0401/snoop-control-unit/scu-registers/scu-control-register?lang=en

support.arm.com

https://codeberg.org/thejpster/hello-de0-nano-soc

codeberg.org