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OR1K Marocchino A Tomasulo Implementation

stffrdhrn.github.io · published 21 October 2019

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https://openrisc.io
openrisc.io
https://en.wikipedia.org/wiki/Tomasulo_algorithm
en.wikipedia.org
https://en.wikipedia.org/wiki/P5_(microarchitecture
en.wikipedia.org
https://arstechnica.com/features/2004/07/pentium-1/
arstechnica.com
http://oldhome.schmorp.de/doc/opt-pairing.html
oldhome.schmorp.de
https://en.wikipedia.org/wiki/Pentium_Pro
en.wikipedia.org
https://en.wikipedia.org/wiki/Reservation_station
en.wikipedia.org
https://en.wikipedia.org/wiki/Re-order_buffer
en.wikipedia.org
https://en.wikipedia.org/wiki/Instruction_pipelining
en.wikipedia.org
https://en.wikipedia.org/wiki/Hazard_(computer_architecture
en.wikipedia.org
https://github.com/openrisc/or1k_marocchino/blob/master/rtl/verilog/or1k_marocchino_oman.v
github.com
https://github.com/openrisc/or1k_marocchino/blob/master/rtl/verilog/or1k_marocchino_cpu.v
github.com
https://meltdownattack.com/
meltdownattack.com
https://twitter.com/stffrdhrn
twitter.com
https://courses.cs.washington.edu/courses/csep548/06au/lectures.html
courses.cs.washington.edu
https://courses.cs.washington.edu/courses/cse548/06wi/slides/reorderBuf.pdf
courses.cs.washington.edu
https://cseweb.ucsd.edu/classes/wi13/cse240a/
cseweb.ucsd.edu
https://en.wikipedia.org/wiki/Intel_Core_(microarchitecture
en.wikipedia.org