corpus.blog
56,966 blogs · [ { "id": "01a0c505-a741-701a-8ff6-fef762a681e0", "title": "When the Debugger Lies", "url": "https://danielmangum.com/posts/when-the-debugger-lies/", "published_at": "2026-09-18T07:41:34+00:00" }, { "id": "01a08767-3962-7063-a1e7-026511feec6c", "title": "Farewell Golioth... and Hello Nordic!", "url": "https://danielmangum.com/posts/farewell-golioth-hello-nordic/", "published_at": "2026-08-24T07:41:34+00:00" }, { "id": "01a08767-3962-7063-a1e7-0265126a2cc8", "title": "The Simple Elegance of the Integrated Timing Belt Loopback Fastener", "url": "https://danielmangum.com/posts/integrated-timing-belt-loopback-fastener/", "published_at": "2026-07-31T07:41:34+00:00" }, { "id": "01a08767-3962-7063-a1e7-0265132f0225", "title": "Leadership Lessons from The Odyssey", "url": "https://danielmangum.com/posts/odyssey-leadership-lessons/", "published_at": "2026-07-27T07:41:34+00:00" }, { "id": "01a08767-3962-7063-a1e7-026514095185", "title": "JLink JTAG Access on the Pinecil", "url": "https://danielmangum.com/posts/jlink-jtag-pinecil/", "published_at": "2026-05-30T07:41:34+00:00" }, { "id": "01a08767-3962-7063-a1e7-02651465514d", "title": "Floating Point Fun on Cortex-M Processors", "url": "https://danielmangum.com/posts/floating-point-cortex-m/", "published_at": "2026-04-16T07:41:34+00:00" }, { "id": "01a08767-3962-7063-a1e7-02651525feb9", "title": "PSA Crypto: The P is for Portability", "url": "https://danielmangum.com/posts/psa-crypto-portability/", "published_at": "2026-04-10T07:41:34+00:00" }, { "id": "01a08767-3962-7063-a1e7-0265153f3a8a", "title": "Fooling Go's X.509 Certificate Verification", "url": "https://danielmangum.com/posts/fooling-go-x509-certificate-verification/", "published_at": "2026-03-01T07:41:34+00:00" }, { "id": "01a08767-3962-7063-a1e7-0265154ac57b", "title": "Making Ferrite Core Inductors at Home", "url": "https://danielmangum.com/posts/making-ferrite-core-inductors-home/", "published_at": "2026-02-01T07:41:34+00:00" }, { "id": "01a08767-3962-7063-a1e7-026515beb7a8", "title": "3,500 Miles in 2025", "url": "https://danielmangum.com/posts/3500-miles-2025/", "published_at": "2026-01-19T07:41:34+00:00" }, { "id": "01a08767-3962-7063-a1e7-02651601271c", "title": "Fixing My System76 Laptop in 20 Minutes or Less", "url": "https://danielmangum.com/posts/fix-system76-laptop-20-min/", "published_at": "2025-12-30T07:41:34+00:00" }, { "id": "01a08767-3963-7146-93ad-27fda57beb1b", "title": "Determining Current Arm Cortex-M Security State with GDB", "url": "https://danielmangum.com/posts/arm-cortex-m-security-state-gdb/", "published_at": "2025-12-24T07:41:34+00:00" }, { "id": "01a08767-3963-7146-93ad-27fda6019aff", "title": "Make it Possible, Then Make it Normal", "url": "https://danielmangum.com/posts/possible-then-normal/", "published_at": "2025-11-09T07:41:34+00:00" }, { "id": "01a08767-3963-7146-93ad-27fda66badb0", "title": "Interesting SPI Routing with iCE40 FPGAs", "url": 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"2024-12-24T07:41:34+00:00" }, { "id": "01a08767-3963-7146-93ad-27fdaba7bcf8", "title": "USB UART on the Thingy:91 X", "url": "https://danielmangum.com/posts/usb-uart-thingy91-x/", "published_at": "2024-12-15T07:41:34+00:00" }, { "id": "01a08767-3963-7146-93ad-27fdac5cc682", "title": "This Website is Hosted on Bluesky", "url": "https://danielmangum.com/posts/this-website-is-hosted-on-bluesky/", "published_at": "2024-11-24T07:41:34+00:00" }, { "id": "01a08767-3963-7146-93ad-27fdac8a4ef6", "title": "USB On-The-Go on the ESP32-S3", "url": "https://danielmangum.com/posts/usb-otg-esp32s3/", "published_at": "2024-11-11T07:41:34+00:00" }, { "id": "01a08767-3963-7146-93ad-27fdad858f01", "title": "Is It Better to Fail Spectacularly?", "url": "https://danielmangum.com/posts/better-to-fail-spectacularly/", "published_at": "2024-10-20T07:41:34+00:00" }, { "id": "01a08767-3963-7146-93ad-27fdae4b1e6a", "title": "The Taxonomy of Hardware Security Mechanisms", "url": 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"published_at": "2024-03-10T07:41:34+00:00" }, { "id": "01a08767-3963-7146-93ad-27fdb1482eee", "title": "RISC-V Bytes: Accessing the Pinecil UART with picoprobe", "url": "https://danielmangum.com/posts/risc-v-bytes-accessing-pinecil-uart-picoprobe/", "published_at": "2024-01-29T06:10:34+00:00" }, { "id": "01a08767-3963-7146-93ad-27fdb1a94b20", "title": "RISC-V Bytes: Soldering the Pinecil Breakout Board", "url": "https://danielmangum.com/posts/risc-v-bytes-soldering-pinecil-breakout-board/", "published_at": "2024-01-22T06:10:34+00:00" }, { "id": "01a08767-3963-7146-93ad-27fdb1e7ad8a", "title": "Reflections on Running 3,000 Miles in 2023", "url": "https://danielmangum.com/posts/3000-miles-2023/", "published_at": "2024-01-02T06:10:34+00:00" }, { "id": "01a08767-3963-7146-93ad-27fdb2d7f477", "title": "Understanding Every Byte in a WASM Module", "url": "https://danielmangum.com/posts/every-byte-wasm-module/", "published_at": "2023-12-22T06:10:34+00:00" }, { "id": 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"published_at": "2023-11-03T06:10:34+00:00" }, { "id": "01a08767-3963-7146-93ad-27fdb79c9a0e", "title": "A Particularly Gnarly Case of Go’s Non-Nil Interfaces", "url": "https://danielmangum.com/posts/go-gnarly-non-nil-interfaces/", "published_at": "2023-10-20T06:10:34+00:00" }, { "id": "01a08767-3963-7146-93ad-27fdb83a899c", "title": "How LUTs Are Used as Storage Elements on an FPGA", "url": "https://danielmangum.com/posts/how-luts-used-storage-fpga/", "published_at": "2023-10-14T06:10:34+00:00" }, { "id": "01a08767-3963-7146-93ad-27fdb8bc7c80", "title": "The Value of Livestreaming Long-Term Projects", "url": "https://danielmangum.com/posts/value-livestreaming-long-term/", "published_at": "2023-10-06T06:10:34+00:00" }, { "id": "01a08767-3963-7146-93ad-27fdb96f991f", "title": "When Does Vivado Infer BRAM?", "url": "https://danielmangum.com/posts/when-vivado-infer-bram/", "published_at": "2023-10-01T06:10:34+00:00" }, { "id": "01a08767-3963-7146-93ad-27fdb9a0f4ed", "title": "Microprocessors Are Tiny, But They Can’t Fit in Your Head", "url": "https://danielmangum.com/posts/microprocessors-tiny-cant-fit-in-head/", "published_at": "2023-09-02T06:10:34+00:00" }, { "id": "01a08767-3963-7146-93ad-27fdb9d3f080", "title": "A Brief Retrospective on SPARC Register Windows", "url": "https://danielmangum.com/posts/retrospective-sparc-register-windows/", "published_at": "2023-08-21T06:10:34+00:00" }, { "id": "01a08767-3963-7146-93ad-27fdba20a5a3", "title": "How To Dissect a Critical HackerNews Comment", "url": "https://danielmangum.com/posts/how-to-dissect-critical-hackernews/", "published_at": "2023-08-09T06:10:34+00:00" }, { "id": "01a08767-3963-7146-93ad-27fdba368f6b", "title": "A Single-Cycle 64-Bit RISC-V Register File", "url": "https://danielmangum.com/posts/single-cycle-rv64-register-file/", "published_at": "2023-08-04T06:10:34+00:00" }, { "id": "01a08767-3963-7146-93ad-27fdba384493", "title": "Single-Cycle and Multicycle Do Not Describe Processor Performance", "url": "https://danielmangum.com/posts/single-cycle-multicycle-processor-performance/", "published_at": "2023-07-28T06:10:34+00:00" }, { "id": "01a08767-3963-7146-93ad-27fdbb0ae664", "title": "Why Create a New Instruction Set Architecture?", "url": "https://danielmangum.com/posts/why-create-new-isa/", "published_at": "2023-07-21T06:10:34+00:00" }, { "id": "01a08767-3963-7146-93ad-27fdbb8f7ec7", "title": "A Three Year Bet on Chip Design", "url": "https://danielmangum.com/posts/a-three-year-bet-on-chip-design/", "published_at": "2023-07-19T06:10:34+00:00" }, { "id": "01a08767-3963-7146-93ad-27fdbbf89b9d", "title": "RISC-V Bytes: Semihosting with Zephyr on an ESP32", "url": "https://danielmangum.com/posts/risc-v-bytes-semihosting-zephyr-esp32/", "published_at": "2023-05-30T06:10:34+00:00" }, { "id": "01a08767-3963-7146-93ad-27fdbc1ad79f", "title": "RISC-V Bytes: Zephyr Before Main", "url": "https://danielmangum.com/posts/risc-v-bytes-zephyr-before-main/", "published_at": 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"RISC-V Bytes: Go 1.19's Register-Based Calling Convention", "url": "https://danielmangum.com/posts/risc-v-bytes-go-1-19-register-calling/", "published_at": "2022-08-08T06:10:34+00:00" }, { "id": "01a08767-3963-7146-93ad-27fdc26ab399", "title": "RISC-V Bytes: Stack Use After Return in C, Go, and Rust", "url": "https://danielmangum.com/posts/risc-v-bytes-stack-use-after-return/", "published_at": "2022-08-01T06:10:34+00:00" }, { "id": "01a08767-3963-7146-93ad-27fdc3292543", "title": "Dynamically Linked Programs with Binfmt_misc", "url": "https://danielmangum.com/risc-v-tips/2022-07-03-dynamically-linked-binfmt-misc/", "published_at": "2022-07-03T06:10:34+00:00" }, { "id": "01a08767-3963-7146-93ad-27fdc3acd3b3", "title": "Sandbox Programmers", "url": "https://danielmangum.com/posts/sandbox-programmers/", "published_at": "2022-05-01T06:10:34+00:00" }, { "id": "01a08767-3963-7146-93ad-27fdc46a7e56", "title": "Opening a UDP Socket in RISC-V Assembly", "url": "https://danielmangum.com/risc-v-tips/2022-05-14-opening-a-udp-socket-risc-v/", "published_at": "2022-04-14T06:10:34+00:00" }, { "id": "01a08767-3963-7146-93ad-27fdc4a39c73", "title": "Graceful Shutdown of Responsibilities in a Growing Organization", "url": "https://danielmangum.com/posts/graceful-shutdown-responsibilities-organization/", "published_at": "2022-02-13T06:10:34+00:00" }, { "id": "01a08767-3963-7146-93ad-27fdc5660931", "title": "The Missing Kubernetes Type System", "url": "https://danielmangum.com/posts/the-missing-kubernetes-type-system/", "published_at": "2022-02-07T06:10:34+00:00" }, { "id": "01a08767-3963-7146-93ad-27fdc615b890", "title": "RISC-V Bytes: Rust Cross-Compilation", "url": "https://danielmangum.com/posts/risc-v-bytes-rust-cross-compilation/", "published_at": "2022-01-30T06:10:34+00:00" }, { "id": "01a08767-3963-7146-93ad-27fdc64a6e11", "title": "Load-Reserved/Store-Conditional Release & Acquire Semantics", "url": "https://danielmangum.com/risc-v-tips/2022-01-17-lr-sc-release-acquire/", "published_at": "2022-01-17T06:10:34+00:00" }, { "id": "01a08767-3963-7146-93ad-27fdc7170bd2", "title": "RVWMO Preserved Program Order Rule 2", "url": "https://danielmangum.com/risc-v-tips/2022-01-09-rvwmo-ppo-rule-2/", "published_at": "2022-01-09T06:10:34+00:00" }, { "id": "01a08767-3963-7146-93ad-27fdc7c1f692", "title": "RVWMO Preserved Program Order Rule 1", "url": "https://danielmangum.com/risc-v-tips/2022-01-06-rvwmo-ppo-rule-1/", "published_at": "2022-01-06T06:10:34+00:00" }, { "id": "01a08767-3963-7146-93ad-27fdc837a10e", "title": "RISC-V Weak Memory Ordering", "url": "https://danielmangum.com/risc-v-tips/2022-01-05-rvwmo/", "published_at": "2022-01-05T06:10:34+00:00" }, { "id": "01a08767-3963-7146-93ad-27fdc8c9d411", "title": "The Zmmul Extension", "url": "https://danielmangum.com/risc-v-tips/2022-01-04-the-zmmul-extension/", "published_at": "2022-01-04T06:10:34+00:00" }, { "id": "01a08767-3963-7146-93ad-27fdc908ff47", "title": "Instruction-Address-Misaligned Exceptions", "url": "https://danielmangum.com/risc-v-tips/2022-01-02-instruction-address-misaligned-exceptions/", "published_at": "2022-01-02T06:10:34+00:00" }, { "id": "01a08767-3963-7146-93ad-27fdc9e8729a", "title": "Fine-Grained Address-Translation Cache Invalidation (Svinval)", "url": "https://danielmangum.com/risc-v-tips/2022-01-01-fine-grained-address-translation-cache-invalidation/", "published_at": "2022-01-01T06:10:34+00:00" }, { "id": "01a08767-3963-7146-93ad-27fdcabafcf4", "title": "NAPOT Translation Continuity (Svnapot)", "url": "https://danielmangum.com/risc-v-tips/2021-12-31-napot-translation-continuity/", "published_at": "2021-12-31T06:10:34+00:00" }, { "id": "01a08767-3963-7146-93ad-27fdcadd67fc", "title": "Page-Based Memory Types (Svpbmt)", "url": "https://danielmangum.com/risc-v-tips/2021-12-30-page-based-memory-types/", "published_at": "2021-12-30T06:10:34+00:00" }, { "id": "01a08767-3963-7146-93ad-27fdcbcd8edc", "title": "Memory Ordering Instructions: FENCE.I", "url": "https://danielmangum.com/risc-v-tips/2021-12-29-memory-ordering-fencei/", "published_at": "2021-12-29T06:10:34+00:00" }, { "id": "01a08767-3963-7146-93ad-27fdcca28db9", "title": "Memory Ordering Instructions: FENCE", "url": "https://danielmangum.com/risc-v-tips/2021-12-28-memory-ordering-fence/", "published_at": "2021-12-28T06:10:34+00:00" }, { "id": "01a08767-3963-7146-93ad-27fdcd300281", "title": "RISC-V Bytes: Privilege Levels", "url": "https://danielmangum.com/posts/risc-v-bytes-privilege-levels/", "published_at": "2021-12-27T06:10:34+00:00" }, { "id": "01a08767-3963-7146-93ad-27fdcd636698", "title": "Non-Maskable Interrupts", "url": "https://danielmangum.com/risc-v-tips/2021-12-26-non-maskable-interrupts/", "published_at": "2021-12-26T06:10:34+00:00" }, { "id": "01a08767-3963-7146-93ad-27fdcddf3960", "title": "CSR Clear and Set Bits Instructions", "url": "https://danielmangum.com/risc-v-tips/2021-12-25-csr-clear-set-bits/", "published_at": "2021-12-25T06:10:34+00:00" }, { "id": "01a08767-3963-7146-93ad-27fdce0778d5", "title": "4-Byte Aligned Trap Vectors", "url": "https://danielmangum.com/risc-v-tips/2021-12-24-4-byte-aligned-trap-vectors/", "published_at": "2021-12-24T06:10:34+00:00" }, { "id": "01a08767-3963-7146-93ad-27fdce719900", "title": "ld Default Entry Point", "url": "https://danielmangum.com/risc-v-tips/2021-12-23-ld-default-entry-point/", "published_at": "2021-12-23T06:10:34+00:00" }, { "id": "01a08767-3963-7146-93ad-27fdcee3d142", "title": "Pipelined Trap Precision", "url": "https://danielmangum.com/risc-v-tips/2021-12-22-trap-precision/", "published_at": "2021-12-22T06:10:34+00:00" }, { "id": "01a08767-3963-7146-93ad-27fdcf6c39ab", "title": "SiFive P650", "url": "https://danielmangum.com/risc-v-tips/2021-12-20-sifive-p650/", "published_at": "2021-12-20T06:10:34+00:00" }, { "id": "01a08767-3963-7146-93ad-27fdcfdff1fb", "title": "Instruction Format Regularity", "url": "https://danielmangum.com/risc-v-tips/2021-12-18-instruction-format-regularity/", "published_at": "2021-12-18T06:10:34+00:00" }, { "id": "01a08767-3964-72c3-906c-5f57ebde8f72", "title": "Atomicity PMAs", "url": "https://danielmangum.com/risc-v-tips/2021-12-14-atomicity-pmas/", "published_at": "2021-12-14T06:10:34+00:00" }, { "id": "01a08767-3964-72c3-906c-5f57ec2a1d66", "title": "Physical Memory Attributes (PMAs)", "url": "https://danielmangum.com/risc-v-tips/2021-12-12-physical-memory-attributes/", "published_at": "2021-12-13T06:10:34+00:00" }, { "id": "01a08767-3964-72c3-906c-5f57ece9f587", "title": "Access and Privilege in CSR Addresses", "url": "https://danielmangum.com/risc-v-tips/2021-12-12-access-privilege-csr-addresses/", "published_at": "2021-12-12T06:10:34+00:00" }, { "id": "01a08767-3964-72c3-906c-5f57ed23c390", "title": "OpenTitan Assembly Style Guide", "url": "https://danielmangum.com/risc-v-tips/2021-12-11-opentitan-assembly-style-guide/", "published_at": "2021-12-11T06:10:34+00:00" }, { "id": "01a08767-3964-72c3-906c-5f57edad935c", "title": "xv6 Teaching Operating System", "url": "https://danielmangum.com/risc-v-tips/2021-12-10-xv6-teaching-os/", "published_at": "2021-12-10T06:10:34+00:00" }, { "id": "01a08767-3964-72c3-906c-5f57edcccee9", "title": "Interrupt Controllers", "url": "https://danielmangum.com/risc-v-tips/2021-12-09-interrupt-controllers/", "published_at": "2021-12-09T06:10:34+00:00" }, { "id": "01a08767-3964-72c3-906c-5f57ee6007ee", "title": "The Hypervisor Extension", "url": "https://danielmangum.com/risc-v-tips/2021-12-08-hypervisor-extension/", "published_at": "2021-12-08T06:10:34+00:00" }, { "id": "01a08767-3964-72c3-906c-5f57ef491a0d", "title": "Open Hardware for the Open Cloud", "url": "https://danielmangum.com/risc-v-tips/2021-12-02-open-hardware-for-the-open-cloud/", "published_at": "2021-12-02T06:10:34+00:00" }, { "id": "01a08767-3964-72c3-906c-5f57f0194d26", "title": "Supervisor Trap Base Address Register", "url": "https://danielmangum.com/risc-v-tips/2021-12-01-supervisor-trap-base-address/", "published_at": "2021-12-01T06:10:34+00:00" }, { "id": "01a08767-3964-72c3-906c-5f57f095bc9e", "title": "Supervisor Memory Management Fence Instruction", "url": "https://danielmangum.com/risc-v-tips/2021-11-30-supervisor-mm-fence/", "published_at": "2021-11-30T06:10:34+00:00" }, { "id": "01a08767-3964-72c3-906c-5f57f115d287", "title": "Sv32 Megapages", "url": "https://danielmangum.com/risc-v-tips/2021-11-29-sv-32-megapages/", "published_at": "2021-11-29T06:10:34+00:00" } ] posts Claim your blog
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Daniel Mangum

danielmangum.com

2026

When the Debugger Liesoriginal ↗
18 Sept 2026
Farewell Golioth... and Hello Nordic!original ↗
24 Aug 2026
The Simple Elegance of the Integrated Timing Belt Loopback Fasteneroriginal ↗
31 Jul 2026
Leadership Lessons from The Odysseyoriginal ↗
27 Jul 2026
JLink JTAG Access on the Pineciloriginal ↗
30 May 2026
Floating Point Fun on Cortex-M Processorsoriginal ↗
16 Apr 2026
PSA Crypto: The P is for Portabilityoriginal ↗
10 Apr 2026
Fooling Go's X.509 Certificate Verificationoriginal ↗
1 Mar 2026
Making Ferrite Core Inductors at Homeoriginal ↗
1 Feb 2026
3,500 Miles in 2025original ↗
19 Jan 2026

2025

Fixing My System76 Laptop in 20 Minutes or Lessoriginal ↗
30 Dec 2025
Determining Current Arm Cortex-M Security State with GDBoriginal ↗
24 Dec 2025
Make it Possible, Then Make it Normaloriginal ↗
9 Nov 2025
Interesting SPI Routing with iCE40 FPGAsoriginal ↗
7 Nov 2025
Using a Laptop as an HDMI Monitor for an SBCoriginal ↗
9 Oct 2025
How AI on Microcontrollers Actually Works: Registering Operatorsoriginal ↗
14 Jul 2025
How AI on Microcontrollers Actually Works: The Computation Graphoriginal ↗
7 Jul 2025
How AI on Microcontrollers Actually Works: Operators and Kernelsoriginal ↗
30 Jun 2025
Just Barely Fitting a Full Wi-Fi Stack on the nRF9151original ↗
17 Feb 2025
Accessing the Qualcomm Modem over USB on the RAK5010original ↗
30 Jan 2025

2024

VPR: Arm and RISC-V Inter-Processor Communicationoriginal ↗
31 Dec 2024
VPR: Nordic's First RISC-V Processororiginal ↗
24 Dec 2024
USB UART on the Thingy:91 Xoriginal ↗
15 Dec 2024
This Website is Hosted on Blueskyoriginal ↗
24 Nov 2024
USB On-The-Go on the ESP32-S3original ↗
11 Nov 2024
Is It Better to Fail Spectacularly?original ↗
20 Oct 2024
The Taxonomy of Hardware Security Mechanismsoriginal ↗
29 Sept 2024
Founder Mode for Non-Foundersoriginal ↗
3 Sept 2024
Static Allocation in External RAM on ESP32original ↗
30 Jun 2024
Wireframes are Cheap, Engineering Should Be Toooriginal ↗
15 Jun 2024
The Most Important Skill in Startup Engineering Leadershiporiginal ↗
10 Mar 2024
RISC-V Bytes: Accessing the Pinecil UART with picoprobeoriginal ↗
29 Jan 2024
RISC-V Bytes: Soldering the Pinecil Breakout Boardoriginal ↗
22 Jan 2024
Reflections on Running 3,000 Miles in 2023original ↗
2 Jan 2024

2023

Understanding Every Byte in a WASM Moduleoriginal ↗
22 Dec 2023
Zero to WASI with Clang 17original ↗
19 Dec 2023
Supercon 2023 Day 3: badgecase.iooriginal ↗
6 Nov 2023
Supercon 2023 Day 2: Talks Begin, Hacking Continuesoriginal ↗
5 Nov 2023
Supercon 2023 Day 1: Hello Badgeoriginal ↗
4 Nov 2023
Setting Up Verible for Verilog with Neovimoriginal ↗
3 Nov 2023
A Particularly Gnarly Case of Go’s Non-Nil Interfacesoriginal ↗
20 Oct 2023
How LUTs Are Used as Storage Elements on an FPGAoriginal ↗
14 Oct 2023
The Value of Livestreaming Long-Term Projectsoriginal ↗
6 Oct 2023
When Does Vivado Infer BRAM?original ↗
1 Oct 2023
Microprocessors Are Tiny, But They Can’t Fit in Your Headoriginal ↗
2 Sept 2023
A Brief Retrospective on SPARC Register Windowsoriginal ↗
21 Aug 2023
How To Dissect a Critical HackerNews Commentoriginal ↗
9 Aug 2023
A Single-Cycle 64-Bit RISC-V Register Fileoriginal ↗
4 Aug 2023
Single-Cycle and Multicycle Do Not Describe Processor Performanceoriginal ↗
28 Jul 2023
Why Create a New Instruction Set Architecture?original ↗
21 Jul 2023
A Three Year Bet on Chip Designoriginal ↗
19 Jul 2023
RISC-V Bytes: Semihosting with Zephyr on an ESP32original ↗
30 May 2023
RISC-V Bytes: Zephyr Before Mainoriginal ↗
28 Apr 2023
RISC-V Bytes: Zephyr on the ESP32original ↗
17 Apr 2023
RISC-V Bytes: Exploring a Custom ESP32 Bootloaderoriginal ↗
9 Apr 2023
Do you want to take a leap of faith?original ↗
6 Apr 2023
Where does the kubelet mount volumes?original ↗
18 Mar 2023
K8s ASA: Watching and Cachingoriginal ↗
13 Feb 2023
K8s ASA: The Storage Interfaceoriginal ↗
23 Jan 2023
Welcome to Kubernetes API Server Adventuresoriginal ↗
16 Jan 2023

2022

RISC-V Bytes: Timer Interruptsoriginal ↗
27 Dec 2022
I'm on Mastodonoriginal ↗
18 Dec 2022
RISC-V Bytes: Go 1.19's Register-Based Calling Conventionoriginal ↗
8 Aug 2022
RISC-V Bytes: Stack Use After Return in C, Go, and Rustoriginal ↗
1 Aug 2022
Dynamically Linked Programs with Binfmt_miscoriginal ↗
3 Jul 2022
Sandbox Programmersoriginal ↗
1 May 2022
Opening a UDP Socket in RISC-V Assemblyoriginal ↗
14 Apr 2022
Graceful Shutdown of Responsibilities in a Growing Organizationoriginal ↗
13 Feb 2022
The Missing Kubernetes Type Systemoriginal ↗
7 Feb 2022
RISC-V Bytes: Rust Cross-Compilationoriginal ↗
30 Jan 2022
Load-Reserved/Store-Conditional Release & Acquire Semanticsoriginal ↗
17 Jan 2022
RVWMO Preserved Program Order Rule 2original ↗
9 Jan 2022
RVWMO Preserved Program Order Rule 1original ↗
6 Jan 2022
RISC-V Weak Memory Orderingoriginal ↗
5 Jan 2022
The Zmmul Extensionoriginal ↗
4 Jan 2022
Instruction-Address-Misaligned Exceptionsoriginal ↗
2 Jan 2022
Fine-Grained Address-Translation Cache Invalidation (Svinval)original ↗
1 Jan 2022

2021

NAPOT Translation Continuity (Svnapot)original ↗
31 Dec 2021
Page-Based Memory Types (Svpbmt)original ↗
30 Dec 2021
Memory Ordering Instructions: FENCE.Ioriginal ↗
29 Dec 2021
Memory Ordering Instructions: FENCEoriginal ↗
28 Dec 2021
RISC-V Bytes: Privilege Levelsoriginal ↗
27 Dec 2021
Non-Maskable Interruptsoriginal ↗
26 Dec 2021
CSR Clear and Set Bits Instructionsoriginal ↗
25 Dec 2021
4-Byte Aligned Trap Vectorsoriginal ↗
24 Dec 2021
ld Default Entry Pointoriginal ↗
23 Dec 2021
Pipelined Trap Precisionoriginal ↗
22 Dec 2021
SiFive P650original ↗
20 Dec 2021
Instruction Format Regularityoriginal ↗
18 Dec 2021
Atomicity PMAsoriginal ↗
14 Dec 2021
Physical Memory Attributes (PMAs)original ↗
13 Dec 2021
Access and Privilege in CSR Addressesoriginal ↗
12 Dec 2021
OpenTitan Assembly Style Guideoriginal ↗
11 Dec 2021
xv6 Teaching Operating Systemoriginal ↗
10 Dec 2021
Interrupt Controllersoriginal ↗
9 Dec 2021
The Hypervisor Extensionoriginal ↗
8 Dec 2021
Open Hardware for the Open Cloudoriginal ↗
2 Dec 2021
Supervisor Trap Base Address Registeroriginal ↗
1 Dec 2021
Supervisor Memory Management Fence Instructionoriginal ↗
30 Nov 2021
Sv32 Megapagesoriginal ↗
29 Nov 2021
Next